1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same, more particularly to a method of manufacturing a semiconductor device whose parasitic capacity between wiring is small, and to a semiconductor device.
2. Description of the Related Art
Of the prior art methods of forming wiring of a semiconductor device, there is a well-known technique for processing trench wiring. According to this technique, a trench having a wiring pattern in an interlayer insulating film is formed and the trench is filled with conductive materials, such as a metal and the like. In such a technique for processing the trench wiring, an etching stopper film is used so that the to-be-formed trenches have the same depths uniformly. In general, as the etching stopper film, a silicon nitride film as an insulating film is used (U.S. Pat. No. 4,789,648).
FIGS. 7A to 7F are diagrams each showing a manufacturing step of a semiconductor device by applying the technique for processing trench wiring with using the etching stopper film.
First, a first interlayer insulating film 203 is formed on a semiconductor substrate 201 with a surface area on which first wiring 202 is formed as shown in FIG. 7A. A silicon nitride film as an etching stopper film 204 is formed on the first interlayer insulating film 203 as shown in FIG. 7B. A predetermined area of the etching stopper film 204 is etched. More particularly, only a portion which corresponds to a formation area of a via hole (which will be described later) is selectively etched so as to be removed. An opening part 205 is formed in the etching stopper film 204 (FIG. 7C). Next, a second interlayer insulating film 206 is formed on the first interlayer insulating film 203 and the etching stopper film 204 (FIG. 7D). A wiring trench 207 for forming wiring is formed in a formation area of second wiring by etching the second interlayer insulating film 206. Because the etching stopper film 204 exists, only the second interlayer insulating film 206 is etched. A via hole 208 is formed in the first interlayer insulating film 203 by using the etching stopper film 204 as an etching mask (FIG. 7E). Then, metal materials are laid in the wiring trench 207 and the via hole 208 for forming second wiring 209 so as to complete the semiconductor device (FIG. 7F).
According to such a technique explained above, the etching stopper film 204 is formed above the whole surface of the semiconductor substrate 201 excluding the via hole 208. The etching stopper film 204 necessarily exists between the first wiring 202 and the second wiring 209. In other words, in the above-described manufacturing method, the etching stopper film 204 intervenes between the second wiring 209 and adjacent second wiring 209 (not shown). The etching stopper film 204 is formed of silicon nitride (including silicon oxide nitride).
The silicon nitride film has a higher degree of permittivity than a silicon oxide film which is generally used as an interlayer insulating film. Thus, parasitic capacities between a piece of wiring and another wiring formed on the same layer, and between pieces of wiring formed on different layers are large. Accordingly, a problem arises that the parasitic capacity becomes remarkable in size, as the structure of the wiring is complicated. As the parasitic capacity becomes large in size, reliability in an operation of the semiconductor device decreases.
Accordingly, an object of the present invention is to provide a semiconductor device whose parasitic capacity between wiring is small.
Another object thereof is to provide a manufacturing method of an improved semiconductor device.
In addition to this, further object thereof is to provide a manufacturing method capable of lowering with an easy method the parasitic capacity of the semiconductor device.
In order to achieve the above-described objects, according to the first aspect of the present invention, there is provided a manufacturing method of a semiconductor device, comprising:
forming a first interlayer insulating film on a semiconductor substrate with a surface area on which first wiring is formed;
forming an etching stopper film made with a material different from a material of the first interlayer insulating film on the first interlayer insulating film;
patterning the etching stopper film so as to remove a portion corresponding to a via hole to be formed in the first interlayer insulating film and a portion corresponding to a peripheral section of second wiring to be formed;
forming a second interlayer insulating film on the etching stopper film;
forming a wiring trench in the second interlayer insulating film by etching the second interlayer insulating film;
forming the via hole in the first interlayer insulating film by etching the first interlayer insulating film by using the patterned etching stopper film as a mask; and
forming second wiring connected to the first wiring by laying a conductive material in the via hole and the wiring trench.
In the present invention, the etching stopper film is formed in the wiring trench excluding an area for forming the via hole. An area of the etching stopper film formed between the first wiring and the second wiring is small. Therefore, a parasitic capacity between these wiring formed in different layers becomes small, and the parasitic capacity between those wiring formed in the same layer becomes small.
Each of the first interlayer insulating film and the second interlayer insulating film may comprise a silicon oxide film.
The etching stopper film may comprise an insulating film.
The insulating film may have an etching rate which is smaller than an etching rate of the first interlayer insulating film and of the second interlayer insulating film.
Accordingly, the via hole and the wiring trench may be smoothly formed.
The insulating film may have permittivity which is greater than permittivity of the first interlayer insulating film and of the second interlayer insulating film.
The etching rate of the etching stopper film may become smaller than the etching rate of the interlayer insulating film by using as the etching stopper film an insulting film whose permittivity is greater than permittivity of the interlayer insulating film.
The etching stopper film may comprise an inorganic insulating film.
The etching stopper film may comprise a silicon nitride film or a silicon oxide nitride film.
The etching stopper film may comprise a conductive film.
The conductive film may comprise a metal film or a metal composite film.
An etching rate of the etching stopper film may be lower than an etching rate of the interlayer insulating film, by using the metal film or the metal composite film as the etching stopper film.
A material of the conductive film may comprise a material which is same as a conductive material laid in the vial hole and the wiring trench.
The manufacturing method may further comprise removing the etching stopper film, after the via hole and the wiring trench are formed.
The removing may further include ashing the etching stopper film.
In having such a structure, the etching stopper film may be removed with a photomask which is formed on the second interlayer insulating film for forming the via hole and the wiring trench.
The etching stopper film may comprise an organic insulating film.
The organic insulating film may comprise a photosensitive organic insulating film.
The photosensitive organic insulating film may be patterned only by emitting light, without forming the photomask. That is, if the photosensitive organic insulating film is used as the etching stopper film, the etching stopper film may not only be easily removed, but be easily formed.
The patterning of said etching stopper film may comprise using in a sequential order a first photomask having the pattern corresponding to the via hole and a second photomask having the pattern corresponding to the second wiring.
The patterning of the etching stopper film may include using a photomask which has a pattern corresponding to the via hole and a pattern corresponding to the second wiring.
The patterning of the etching stopper film may further include using a photomask which has a pattern corresponding to the via hole and a pattern corresponding to the second wiring.
According to the second aspect of the present invention, there is provided a semiconductor device comprising:
a first wiring layer;
an interlayer insulating film which is formed on the first wiring layer and which includes via on the first wiring layer;
a dielectric film which is formed on the interlayer insulating film and which comprises a material having permittivity different from permittivity of a material of the interlayer insulating film; and
a second wiring layer which is formed on the dielectric film,
wherein the dielectric film is formed in an area where the second wiring layer is formed and which excludes an area of the via, and
the second wiring is connected to the first wiring via a conductive material laid in the via.
According to the present invention, light emission of a pattern in which two patterns (patterns each corresponding to the via hole and the second wiring) are combined may be performed at once. Due to this, patterning steps may be simply processed.
The dielectric film may be a film having permittivity greater than permittivity of the interlayer insulating film.
The dielectric film may be a conductive film.
The conductive film may be a metal film or a metal composite film.